INV_CRC_VAL=0, RX_DMA_EN=0, CRC_OUT_FLIP=0, XMT_CRC_LRC=0, TX_DMA_EN=0, KILL_CLOCKS=0, CRC_EN=0, SW_RST=0, RCV_EN=0, CWT_EN=0, FLSH_TX=0, FLSH_RX=0, ONACK=0, ANACK=0, STOP_EN=0, RCVR_11=0, IC=0, ICM=0, BWT_EN=0, LRC_EN=0, CRC_IN_FLIP=0, DOZE_EN=0, XMT_EN=0
Control Register
| IC | Inverse Convention 0 (0): Direction convention transfers enabled (default) 1 (1): Inverse convention transfers enabled |
| ICM | Initial Character Mode 0 (0): Initial Character Mode disabled 1 (1): Initial Character Mode enabled (default) |
| ANACK | Auto NACK Enable 0 (0): NACK generation on errors disabled 1 (1): NACK generation on errors enabled (default) |
| ONACK | Overrun NACK Enable 0 (0): NACK generation on overrun is disabled (default) 1 (1): NACK generation on overrun is enabled |
| FLSH_RX | Flush Receiver Bit 0 (0): EMV SIM Receiver normal operation (default) 1 (1): EMV SIM Receiver held in Reset |
| FLSH_TX | Flush Transmitter Bit 0 (0): EMV SIM Transmitter normal operation (default) 1 (1): EMV SIM Transmitter held in Reset |
| SW_RST | Software Reset Bit 0 (0): EMV SIM Normal operation (default) 1 (1): EMV SIM held in Reset |
| KILL_CLOCKS | Kill all internal clocks 0 (0): EMV SIM input clock enabled (default) 1 (1): EMV SIM input clock is disabled |
| DOZE_EN | Doze Enable 0 (0): DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default) 1 (1): DOZE instruction has no effect on EMV SIM module |
| STOP_EN | STOP Enable 0 (0): STOP instruction shuts down all EMV SIM clocks (default) 1 (1): STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card) |
| RCV_EN | Receiver Enable 0 (0): EMV SIM Receiver disabled (default) 1 (1): EMV SIM Receiver enabled |
| XMT_EN | Transmitter Enable 0 (0): EMV SIM Transmitter disabled (default) 1 (1): EMV SIM Transmitter enabled |
| RCVR_11 | Receiver 11 ETU Mode Enable 0 (0): Receiver configured for 12 ETU operation mode (default) 1 (1): Receiver configured for 11 ETU operation mode |
| RX_DMA_EN | Receive DMA Enable 0 (0): No DMA Read Request asserted for Receiver (default) 1 (1): DMA Read Request asserted for Receiver |
| TX_DMA_EN | Transmit DMA Enable 0 (0): No DMA Write Request asserted for Transmitter (default) 1 (1): DMA Write Request asserted for Transmitter |
| INV_CRC_VAL | Invert bits in the CRC Output Value 0 (0): Bits in CRC Output value will not be inverted. 1 (1): Bits in CRC Output value will be inverted. (default) |
| CRC_OUT_FLIP | CRC Output Value Bit Reversal or Flip 0 (0): Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default) 1 (1): Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7} |
| CRC_IN_FLIP | CRC Input Byte’s Bit Reversal or Flip Control 0 (0): Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default) 1 (1): Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation |
| CWT_EN | Character Wait Time Counter Enable 0 (0): Character Wait time Counter is disabled (default) 1 (1): Character Wait time counter is enabled |
| LRC_EN | LRC Enable 0 (0): 8-bit Linear Redundancy Checking disabled (default) 1 (1): 8-bit Linear Redundancy Checking enabled |
| CRC_EN | CRC Enable 0 (0): 16-bit Cyclic Redundancy Checking disabled (default) 1 (1): 16-bit Cyclic Redundancy Checking enabled |
| XMT_CRC_LRC | Transmit CRC or LRC Enable 0 (0): No CRC or LRC value is transmitted (default) 1 (1): Transmit LRC or CRC info when FIFO empties (whichever is enabled) |
| BWT_EN | Block Wait Time Counter Enable 0 (0): Disable BWT, BGT Counters (default) 1 (1): Enable BWT, BGT Counters |